It has been the trend to scale down the sizes of memory cells to increase the integration level and thus memory capacity of a DRAM chip. As the size of DRAMs is decreased, the capacity of the capacitor used in the DRAM is correspondingly decreased.
A memory cell of DRAM typically consists of a storage capacitor and an access transistor. One terminal of the capacitor is connected to the drain of the transistor. The source and the gate of the access transistor are connected to external connection lines, which are referred to as "bit line" and "word line". The other terminal of the capacitor is connected to a reference voltage. Thus, the formation of a DRAM cell comprises the formation of a transistor, the formation of a capacitor, the formation of the contact to the capacitor, and the formation of the connection lines.
The capacitor type is typically a planar capacitor, which is easy to manufacture. With the advent of ultra large scale integrated (ULSI) DRAM devices, the size of the devices have gotten smaller and smaller such that the available area for a single memory cell has become very small. This causes a reduction in the capacitor's area, resulting in the reduction of the cell's capacitance.
For very small memory cells, the planar capacitor is difficult to use reliably. Specifically, as the size of the capacitor decreases, the capacitance of the capacitor also decreases. This results in the capacitor being very susceptible to alpha-particle radiation. Additionally, as the capacitance decreases, the charge held by the storage capacitor must be refreshed often. A simple stacked capacitor can not provide sufficient capacitance, even with the use of special dielectric films as the capacitor insulator.
In the prior art, some methods have tried to solve the above problems. For example, trench-shape capacitors are used to increase the capacitor's area. Reducing the thickness of the capacitor's dielectric film can increase the capacitance of the capacitor, but this approach is limited because of yield and reliability problems.
In recent years, capacitors using hemispherical-grain (HSG) polysilicon and reverse-crown structures have been used. The HSG polysilicon increases the surface area of the capacitor's bottom plate, and therefore the capacitance is increased. Increasing the height of stack cells can increase the capacitance of stack capacitor. However, because the height of the stack cells is higher than peripheral circuits, this causes difficulties for cell planarization and the metal connection to the integrated circuit.
When the dimension of DRAM is close to deep-submicron, a new method for manufacturing small capacitors is needed. The planar size of the crown capacitance is too large for deep-submicron DRAM. The capacitor with hemispherical grain polysilicon can reduce the spacing between capacitor's plates. Further, the use of HSG polysilicon produces electrical leakage between the capacitor's plates. Thus, a method to fabricate a capacitor with HSG polysilicon is needed that solves the leakage problem.